Processor extension logic is utilized to extend a microprocessor's capability.
Typically, this logic is in parallel and accessible by the main processor pipeline. It is often used to perform specific, repetitive, computationally intensive functions thereby freeing up the main processor pipeline.
In conventional microprocessors, there are essentially two types of parallel pipeline architectures: tightly coupled and loosely or decoupled. In the former, instructions are fetched and executed serially in the main processor pipeline. If the instruction is an instruction to be processed by the extension logic, the instruction is sent to that logic.
However, every instruction comes from the main pipeline, thus the two pipelines are said to be tightly coupled. Also, transporting each instruction to be executed by the extension logic with the main instruction pipeline requires significant overhead, reducing the efficiency gains provided by the extension logic.
In the second architecture, the parallel pipeline containing the extension logic is capable of fetching and executing its own instructions. However, control and synchronization becomes difficult when programming a processor having such a decoupled architecture.
Thus, there exists a need for a parallel pipeline architecture that can fully exploit the advantages of parallelism without suffering from the design complexity of loosely or completely decoupled pipelines.